(a) Field of the Invention
The present invention relates to a device and method for plasma display panels (PDPs). More specifically, the present invention relates to a PDP sustain-discharge circuit.
(b) Description of the Related Art
Recently, liquid crystal displays (LCDs), field emission displays (FEDs), and PDPs have been actively developed. From among the flat panel devices the PDPs have better luminance and light emission efficiency compared to the other types of flat panel devices, and also have wider view angles. Therefore, PDPs have come into the spotlight as substitutes for the conventional cathode ray tubes (CRTs) in large displays of greater than 40 inches.
The PDP is a flat display that uses plasma generated via a gas discharge process to display characters or images, and tens to millions of pixels are provided thereon in a matrix format, depending on its size. PDPs are categorized into DC PDPs and AC PDPs, according to supplied driving voltage waveforms and discharge cell structures.
Since the DC PDPs have electrodes exposed in the discharge space, they allow the current to flow in the discharge space while the voltage is supplied, and therefore they problematically require resistors for current restriction. On the other hand, since the AC PDPs have electrodes covered by a dielectric layer, capacitances are naturally formed to restrict the current, and the electrodes are protected from ion shocks in the case of discharging. Accordingly, they have a longer lifespan than the DC PDPs.
In general, a method for driving the AC PDP includes a reset period, an addressing period, and a sustain period. In the reset period, the states of the respective cells are reset in order to smoothly address the cells. In the addressing period, cells that are turned on and the cells that are not turned on in a panel are selected, and wall charges are accumulated in the cells that are turned on (i.e., the addressed cells). In the sustain period, discharge is performed in order to actually display pictures on the addressed cells. When it comes to the sustain period, sustain-discharging pulses are alternately applied to the scan electrodes and the sustain electrodes to sustain the display of the image. In the erase period, the wall charges of the cells are reduced to terminate the sustain period.
In the AC PDP, because scan electrodes and sustain electrodes operate as a capacitive load, capacitance with respect to the scan electrodes and sustain electrodes exists, and the panel is equivalently expressed as a panel capacitor. Reactive power other than power for discharge is necessary in order to apply waveforms for the sustain period to the panel capacitor. Hence, a sustain-discharge circuit includes a power recovery circuit for recovering the reactive power and re-using the same.
L. F. Weber has disclosed a sustain-discharge circuit in U.S. Pat. Nos. 4,866,349 and 5,081,400. The sustain-discharge circuit by Weber includes a power recovery capacitor so that the energy of the panel capacitor is recovered to the power recovery capacitor or the energy charged to the power recovery capacitor is delivered to the panel capacitor, because of the resonance caused by the panel capacitor and an inductor.
In the conventional power recovery circuits, however, it is required to always charge the power recovery capacitor by a half of the sustain-discharging voltage immediately after the light has emitted, and when this is not done, a very large inrush current may be generated when a sustain-discharging pulse begins. Further, 100% energy recovery is impossible due to a turn-on loss of switches and a loss of the circuit itself, such as a switching loss during the recovery process. Hence, a terminal voltage of the panel capacitor may not be increased to the sustain-discharging voltage or decreased to a ground voltage, and accordingly, the switches fail to perform zero voltage switching, but perform hard switching, thereby generating unnecessary power loss and adding stress to the switches. Since the conventional sustain-discharge circuit has a long rising time and falling time of the terminal voltage at the panel capacitor, the discharge may be generated during a rising or falling period of the terminal voltage at the panel capacitor.